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Cache memory
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#	Item
181	Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/ Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2007-09-14 13:31:04 Computing Microprocessors Threads Parallel computing CPU cache Computer memory Multithreading Microarchitecture Threading Computer hardware Computer architecture Central processing unit
182	Transparent Hugepage Support Red Hat Inc. Andrea Arcangeli aarcange at redhat.com KVM Forum 2010 Add to Reading List Source URL: www.linux-kvm.org Language: English - Date: 2015-06-23 18:18:00 Computing Computer memory Red Hat Virtual machines CPU cache Cache Page Red Hat Enterprise Virtualization Hyper-V System software Software Central processing unit
183	DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently∗ Pablo Montesinos, Luis Ceze† and Josep Torrellas Department of Computer Science University of Illinois at Urbana Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2008-03-26 12:09:20 Central processing unit Chunk CPU cache Parallel computing C dynamic memory allocation Computer memory Computing Computer hardware
184	SAP HANA Top Ten Questions for Choosing In-Memory Databases Add to Reading List Source URL: go.sap.com Language: English Information technology management Cache SAP AG Database SAP HANA Data management CPU cache Oracle RAC Database management systems Computing In-memory database
185	Administrivia • Project 1 due right now - Free extension if you are here - Of for SCPD students who watch lecture before midnight • To get extension Add to Reading List Source URL: www.scs.stanford.edu Language: English - Date: 2010-02-19 22:26:45 Computer memory Computer architecture Cache coherency Parallel computing Concurrency Spinlock Readers-writers problem Test-and-set Non-Uniform Memory Access Computing Concurrent computing Concurrency control
186	Towards a Performance- and Energy-Efficient Data Filter Cache Alen Bardizbanyan Magnus Själander Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2013-04-03 06:08:55 Computer memory Cache Computer architecture CPU cache Translation lookaside buffer Microarchitecture Memory hierarchy Lookup table Scratchpad memory Computer hardware Computing Central processing unit
187	A quad-tree based Sparse BLAS implementation for shared memory parallel computers Michele Martone Universit` a di Roma “Tor Vergata”, Italy Add to Reading List Source URL: claudius.ce.uniroma2.it Language: English - Date: 2013-03-15 13:10:13 Sparse matrix Loop nest optimization CPU cache Mathematics Parallel computing Matrix Memory hierarchy Rank Computer memory Computing Cache
188	RCDC: A Relaxed Consistency Deterministic Computer Joseph Devietti Jacob Nelson Tom Bergan Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2011-05-12 02:39:36 Computer hardware Computer memory Transaction processing Central processing unit Parallel computing Memory barrier CPU cache Non-blocking algorithm Thread Computing Concurrency control Computer architecture
189	Administrivia • Project 2 due Thursday - As before, free extension to midnight if you come to class • Use the newsgroup! - Lots of similar questions to cs140-staff Add to Reading List Source URL: www.scs.stanford.edu Language: English - Date: 2010-02-02 18:33:03 Central processing unit Computing Memory management Computer memory Page CPU cache Paging X86 Cache Virtual memory Computer hardware Computer architecture

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